| Description || The LEON core is an open source VHDL implementation of a SPARC V8 core |
| Informations || Go to GAISLER RESEARCH home page for more informations on LEON. |
| Author(s) || Jiri Gaisler |
| Related Link(s) || DRAGONFLY micro core to simplify the design of new IP blocks. |
AMBA Bus System for a synthetic description of the AMBA buses.
FAQ from the leon_sparc mailing list.
The LEON core is an open source VHDL implementation of a full SPARC V8 standard core developed by Jiri Gaisler.
For more information, go to GAISLER RESEARCH home page.
Read also the Collection of frequently asked questions from the leon_sparc mailing list.
The LEON VHDL model, now in its LEON2 1.0.12 version, implement a 32-bit processor conforming to the SPARC V8 architecture. It is designed for embedded applications with the following features on-chip:
- Separate instruction and data caches.
- Interrupt controller.
- Two 24-bit timers.
- Two UARTs.
- Power-down function.
- 16-bit I/O port.
- Flexible memory controller.
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| LEON: Architecture Overview|
Additional modules can easily be added using the on-chip AMBA buses: Advanced High-speed Bus (AHB) and Advanced Peripheral Bus (APB).
Have a look at the AMBA Bus System for a synthetic description of these 2 buses.
The DRAGONFLY micro core will make design of new IP blocks easier, and will try to standardize IP's I/O interfaces.
The idea behind is to ensure the "IP reuse" notion and the "Plug and Play" aspect of IPs.
The VHDL model is fully synthesisable with most synthesis tools and can be implemented on both FPGAs and ASICs. Simulation can be done with all VHDL-87 compliant simulators.
The LEON VHDL model is provided under two licences: This means that you can use LEON as a core in a System on Chip design without having to publish the source code of any additionnal IP-cores you might use.
You must however publish any modifications you made to the LEON core itself as described in the GNU Lesser General Public Licence (LGPL).
The AMBA Bus System defines a bus hierarchy of a system bus and a peripheral bus.
The two buses are linked via a bridge that serves as the master to the peripheral bus slave devices.
The system bus can be 1 or 2 defined buses: the newest AHB, the Advanced High-speed Bus, or else the earlier ASB, the Advanced System Bus. The peripheral, called APB for Advanced Peripheral Bus, is a simpler, lower-speed, low-power bus for slower devices.
The LEON core VHDL model implements the on-chip AMBA version 2.0 AHB/APB buses.
The AMBA Specification is open and free of any charges.
| AHB: Advanced High-speed Bus|
| 2nd generation AMBA system bus. |
Synchronous nonmultiplexed bus.
Separate read - data buses.
Multimaster - arbitrated bus.
32- 64- 128- 256-bit data paths.
32-bit address bus.
Pipelined - split transactions.
Supports bursts (4- 8- 16-beat).
Non-tristate - multiplexer implementation.
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| APB: Advanced Peripheral Bus|
| Peripheral bus for low-speed devices. |
Bridged to AHB system bus.
Synchronous nonmultiplexed bus.
Single master (bridge).
8- 16- 32-bit data bus.
32-bit address bus.
2-cycle transfer - no bursts.
Static - zero power when not in use.
Advanced High-speed Bus
The AHB takes on many characteristics of a standard plug-in bus. It's a multimaster with arbitration, putting the address on the bus, followed by the data. It also supports wait-state insertion and has a data-valid signal (HREADY). This bus differs in that it has separate read (HRDATA) and write (HWDATA) buses. These bus connections are multiplexed, rather than making use of a tristate multiple connection. Advanced Peripheral Bus
AHB supports burst, with 4-, 8-, and 16-beat bursts, as well as undefined-length bursts and single transfers. Bursts can be address wrapped, i.e., staying within a fixed address range. Bursts can't cross a 1-KB address boundary, though. Slaves can insert wait states to adjust its response (up to 16).
All bus operations are initiated by bus masters, which also can serve as a slave. The master-generated address is decoded by a central address decoder that provides a select signal to the addressed bus slave unit. The bus master can "lock" the bus, reserving it with the central arbiter for a series of locked transfers.
The slave unit has the option to terminate a transaction as an error, signal the master to retry, or split the transaction for later completion. Split transactions enable the slave to defer the operation until it's able to accomplish it, thereby releasing the bus for other accesses. The slave signals a split transaction and saves the master number (HMASTER). When ready to complete the transaction, the slave signals the arbiter with the master number. When the arbiter grants bus access to the master, it restarts the transaction. No master can have more then 1 pending split transaction.
Designed to support low-speed peripherals such as UARTs, Timers and PIO, the APB is a simple peripheral bus.
All bus devices are slaves to the master, the bridge to the AHB system bus.
This is a static bus that provides a simple address, with latched address and control signals for easy interfacing.
ARM recommends a dual Read and Write bus implementation, but APB can be implemented with a single tristated data bus.
As a simple bus, the APB doesn't support bursting.
Each transaction consists of 2 cycles: an address cycle (Setup state) and a data cycle (Enable state):
ARM is a registered trademark of ARM Limited. AMBA is a trademark of ARM Limited.
- The bus uses a single clock, PCLK.
- In Setup, the bus brings PSEL and PWRITE up, putting the address on the PADDR address bus.
- In the Enable state, it brings PENABLE up and places data on the PWDATA/PRDATA bus.
- The enable signal, PENABLE, is deasserted on the next clock.