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FAQ: Collection of frequently asked questions from the leon_sparc mailing list

This section answers a several questions that were asked on the leon_sparc mailing list.

The LEON core is an open source VHDL implementation of a full SPARC V8 standard core developed by Jiri Gaisler.
The LEON VHDL model, now in its second version, implement a 32-bit processor conforming to the SPARC V8 architecture.
It is designed for embedded applications with the following features on-chip:
  • Separate instruction and data caches.
  • Interrupt controller.
  • Two 24-bit timers.
  • Two UARTs.
  • Power-down function.
  • Watchdog.
  • 16-bit I/O port.
  • Flexible memory controller.

Additional modules can easily be added using the on-chip AMBA buses: Advanced High-speed Bus (AHB) and Advanced Peripheral Bus (APB).
The VHDL model is fully synthesisable with most synthesis tools and can be implemented on both FPGAs and ASICs.
Simulation can be done with all VHDL-87 compliant simulators.

For more information, go to GAISLER RESEARCH home page.

The LEON VHDL model is provided under two licences: This means that you can use LEON as a core in a System on Chip design without having to publish the source code of any additionnal IP-cores you might use.
You must however publish any modifications you made to the LEON core itself as described in the GNU Lesser General Public Licence (LGPL).

No, you don't have to pay any royalties to Sun, LEON was developed using the SPARC V8 manual from SPARC International and a licence to develop hardware based on the manual.

Back in 1997, SPARC International required a one-time licence fee of $99 to allow you to design a processor according the SPARC manual. Jiri Gaisler did indeed purchase this licence, so LEON was legally developed.
The architecture licence has now been abolished, and designing SPARC processors can be done without any licences what so ever. This is indeed why Jiri Gaisler has selected SPARC, just see how many times Intel, MIPS and ARM have sued companies that developed processors using their architecture.

  • Extracted from http://groups.yahoo.com/group/leon_sparc/message/31 and from http://groups.yahoo.com/group/leon_sparc/message/222

  • SPARC is a registered trademark of SPARC International, Inc.

    Jiri Gaisler said: "I have done a (limited) patent search regarding some design features in LEON, but could not find any patent violations. The closest was the cache streaming function, where MIPS have a patent. However, LEON uses a different re-fill policy and have individual valid bits for each cached word so the MIPS patent is not violated."

  • Extracted from http://groups.yahoo.com/group/leon_sparc/message/31

  • Designing SPARC processors can be done without any licences what so ever. This is indeed why Jiri Gaisler has selected SPARC for the development of LEON, just see how many times Intel, MIPS and ARM have sued companies that developed processors using their architecture.

    For example, in mid-February 2002 the legal battles between Lexra/MIPS and picoTurbo/ARM have both ended with a complete defeat of the two cpu-cloning companies (Lexra and picoTurbo). Both companies have been shut-down and their clients transferred to MIPS/ARM.

    Jiri Gaisler said: "More than ever, I'm happy with the decision to go SPARC. :-) And many thanks to Sun and SPARC International for the open licence!"

  • Extracted from http://groups.yahoo.com/group/leon_sparc/message/1849

  • The LEON processor fits in an Xilinx VIRTEX XCV300 (or upper) or in an Altera FLEX 10K200 or APEX 20K200 (or upper).

  • Read http://groups.yahoo.com/group/leon_sparc/message/1052 and http://groups.yahoo.com/group/leon_sparc/message/1137

  • The 2 commonly used boards on this list are:
    Another interesting prototyping board is the Xilinx Virtex-E FPGA Development Kit from Avnet which has a XCV1000E, 64 MB SDRAM, 32 MB Flash, PCI, Ethernet 10/100, RS232 and many more interfaces. BEWARE, you should have to design an SDRAM controller IP for the LEON core. (Read http://groups.yahoo.com/group/leon_sparc/message/1301).

    Another interesting prototyping board is the APS-V240 Virtex PC104 FPGA Development Board & Kits from APS which has a XCV300 to XCV800, 256K x 18 ZBT SRAM, 2 x RS232. (Read http://groups.yahoo.com/group/leon_sparc/message/1364).

    Realize yourself your custom LEON Virtex prototyping board.

    Yes, Jiri Gaisler designs a LEON simulator called TSIM. With it, you can simulate and debug completely non-intrusively and through any part of the code. TSIM is available in two configurations: ERC32 or LEON emulation.

    TSIM provides several unique features:
    • Accurate and cycle-true emulation of ERC32 and LEON processors
    • .
    • Superior performance: +10 MIPS on standard PC (PIII@933MHz)
    • .
    • Accelerated processor standby mode, allowing faster-than-realtime simulation speeds.
    • .
    • Standalone operation and remote connection to GNU debugger (gdb)
    • .
    • 64-bit time for unlimited simulation periods
    • .
    • Loadable modules to include user-defined I/O devices!
    • .
    • Check-pointing capability to save and restore complete simulator state
    • .

    The TSIM evaluation software is provided under the TSIM evaluation license.

    The LEON processor will usually boot from its internal bootstrap code called bprom (see file leon-x.x.x/pmon/bprom.c). The size of this bootstrap code is less than 1 KByte and is completely integrated into the VHDL code.

    At power-up of LEON, this program does the following things:
    • Initialization of PSR and WIM registers
    • .
    • Initialization of Instruction and Data caches
    • .
    • Initialization of UARTs 1 and 2
    • .
    • Initialization of Timer 1
    • .
    • Configuration of the RAM memory access (especially MEMORY Configuration Register 2)
      • Auto-detection of the RAM bus width
      • .
      • Auto-detection of the number of RAM bank
      • .
      • Auto-detection of the size of each RAM bank
      • .
    • Initialization of the Stack pointer
    • .
    • Display on UART 1 the result of the RAM auto-configuration (e.g. for TSIM, write the string: LEON-1: 1*4096K 32-bit memory)
    • .
    • Wait for the download, through the UART 1 serial link, of a S-Record program
    • .

    To download your application program into LEON's RAM, use the send file submenu of your terminal application (such as HyperTerminal or TeraTerm).

  • Read http://groups.yahoo.com/group/leon_sparc/message/1701

  • When an application terminates, it halts the LEON processor by putting it in error mode.

  • Read http://groups.yahoo.com/group/leon_sparc/message/1752

  • Yes, It is only available into LEON-2.

    The new debug support unit provides a completely non-intrusive debug environment on real target hardware, similar to what is availble with TSIM. A debug monitor (DSUMON) to control the DSU is available as has in fact a similar interface as TSIM. DSUMON can also work as a gdb gateway, allowing full source-level debugging with gdb. Note that with the DSU, a boot-prom is not longer needed since the debug mode can be entered directly at reset and DSUMON will auto-probe the system and configure the memory controller, uarts and timers.

  • Read http://groups.yahoo.com/group/leon_sparc/message/1820

  • No. Use the on-chip debug support (DSU) provided with LEON-2.

    Yes, Atmel-Nantes (FRANCE) has manufactured what the first LEON silicon. The device uses the LEON-FT model, and was manufactured on 0.35 CMOS.

  • Read http://groups.yahoo.com/group/leon_sparc/message/801 and http://groups.yahoo.com/group/leon_sparc/message/805

  • 2 other implementations are known:

    February     1, 2001            EETIMES.com: Momentum builds for open-source processors
    January     16, 2001            Microprocessor Report: A GNU SPARC?. (Read http://groups.yahoo.com/group/leon_sparc/message/631)
    December 15, 2000            EETIMES.com: Metaflow builds SoC platform on open-source core
    December   5, 2000            Atmel news: Atmel / CNES and ESA Sign 3-year Agreement to Develop Next-generation ICs for [...]
    November   2, 2000            iRoC Technologies news: iRoC Technologies announces the first ever Robust IP: a 32 bit RISC processor unit
    March           6, 2000            EETIMES.com: European Space Agency launches free Sparc-like core

    The home page of LEON: GAISLER RESEARCH.

    The LEOX Project: Free Hardware and Software Resources for System on Chip

    Digital Dictation Machine: http://www.ra.informatik.uni-stuttgart.de/Leon/. (Read http://groups.yahoo.com/group/leon_sparc/message/618)

    AMBA Interface for InSilicon PCI core: http://www.estec.esa.nl/microelectronics/core/. (Read http://groups.yahoo.com/group/leon_sparc/message/393)

    CAN Controller (HurriCANe): ftp://ftp.estec.esa.nl/pub/ws/wsd/CAN/can.htm. (Read http://groups.yahoo.com/group/leon_sparc/message/333)

    AMBA Bus DMA Controller: http://www.ee.surrey.ac.uk/Personal/ee71gm/project.html. (Read http://groups.yahoo.com/group/leon_sparc/message/1106)

    Technical SPARC CPU Resources: http://www.users.qwest.net/~eballen1/sparc.tech.links.html. (Read http://groups.yahoo.com/group/leon_sparc/message/1144)

    Note: Except where otherwise specified, the content of the documents below are offered to the public under the GNU Free Documentation License.
                  It may be redistributed or republished only under the terms of that license.

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